Show description

A common feature of these VLSI-based multipliers (and many VLSI-based systems) is the repetitive organization of the physical layout. Repetitive parallel arrays of abutted adder cells, pipelined at each bit (a register placed between each adder cell), provide worst case path delays of only a single adder and a register delay (TC-Q and TSet-up), permitting very high multiplication throughput. Specialized architectures, which are beyond the scope of this article, such as carry save addition, are used to improve the throughput of these VLSI-based multipliers (11,56,143–146).

50,82,85–90,100). The strategy used is to construct binary tree-like structures with the clock pins at the leaf nodes. Minimal skew clock distribution networks are created using a recursive bottom-up approach. At each of the clock pins of the registers, which represent the leaves of the clock distribution tree, a clock net is defined. The point where two zero-skew clock nets connect is chosen so that the effective delay from that point to each clocked register is identical (within the accuracy of the delay model).

This increased capacitance of the H-tree structure exemplifies an important tradeoff between clock delay and clock skew in the design of high-speed clock distribution networks. Symmetric structures are used to minimize clock skew; however, an increase in clock signal delay is incurred. Therefore, the increased clock delay must be considered when choosing between buffered tree and H-tree clock distribution networks. Also, because clock skew affects only sequentially adjacent registers, the obvious advantages to using highly symmetric structures to distribute clock signals are significantly degraded.