Compiler Construction: 16th International Conference, CC by Liza Fireman, Erez Petrank, Ayal Zaks (auth.), Shriram

By Liza Fireman, Erez Petrank, Ayal Zaks (auth.), Shriram Krishnamurthi, Martin Odersky (eds.)

This ebook constitutes the refereed complaints of the sixteenth overseas convention on Compiler building, CC 2007, held in Braga, Portugal, in March 2007 as a part of ETAPS 2007, the eu Joint meetings on conception and perform of Software.

The 15 revised complete papers offered have been rigorously reviewed and chosen from 60 submissions. The papers are geared up in topical sections on structure, rubbish assortment and software research, check in allocation, and application analysis.

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From the partition obtained from the heuristic or CPLEX solver, we derive the declaration order of the arrays (with appropriate padding) to enforce the partition to different memory banks. We also make necessary modifications to accommodate arrays whose sizes are greater than the memory banks. We have used Simple-Scalar[16] to simulate the execution of the benchmark programs. The benchmarks with modified array declaration order, are compiled using the PISA tool-chain compiler provided along with the Simple-Scalar distribution with -O2 optimizations.

StarCore, Inc. SC140 DSP Core Reference Manual. Atlanta, GA, 2001. 18. V. Zivojnovic, J. Velarde, C. Schager, and H. Meyr. DSPStone - A DSP oriented Benchmarking Methodology. In Proceedings of International Conference on Signal Processing Applications and Technology, 1994. An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures K. Shyam1 and R. in Abstract. This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks and various lowpower operating modes for each of these banks.

According to the above Maximum Weight Path Cover 1 We introduce the metric bank-cycle (similar to man-months) to collectively represent the number of memory banks and the cycles for which they remain active. 36 K. Shyam and R. Govindarajan MWPC, arrays a and b will be allocated to memory bank M 1 and c and d to memory bank M 2. For this allocation, the memory banks that are active in each loop and the bank-cycles for which the memory is active are shown in Table 1. We see that memory is active for a total of 26N bank-cycles.

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