Data Converters for Wireless Standards (The International by Chunlei Shi

By Chunlei Shi

This article provides the layout of information converters for rising criteria and introduces the underlying circuit layout ideas. it really is a superb reference for IC and combined sign designers, layout managers and venture leaders in undefined, really these within the instant semiconductor undefined.

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Extra info for Data Converters for Wireless Standards (The International Series in Engineering and Computer Science)

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3 Gain error: Defined as the difference at the full-scale value between the ideal and actual transfer curves when the offset error has been reduced to zero. 16 DATA CONVERTERS FOR WIRELESS STANDARDS 4 INL: Measured as the maximum deviation from a straight-line approximation after the offset and gain error have been removed. 5 DNL: Defined as the maximum deviation in analog step size from 1 LSB. However, the traditional performance parameters can not be directly applied to telecommunication applications.

Overview of Wireless Receiver Architectures 4. 13 Summary In this chapter, different wireless receiver architectures are briefly introduced and compared. In the following chapters, novel techniques will be investigated to design low-power/low-voltage CMOS data converters (analog-to-digital converters and digital-to-analog converters) for several different wireless applications such as WCDMA, WLAN, Bluetooth, HomeRF, etc. It is worthy to note that although all the circuits discussed in this book are originally designed for zero-IF receivers, they can also be used in other receiver architectures.

The 12-bit digital codes from six stages are passed to the digital correction circuit where the 7 effective bits are generated. 2. 5-bit sub-DAC and an Prototype Design:ADC for WLAN(DSSS)/WCDMA 41 interstage amplifier with gain of 2. This circuit operates at a two-phase clock. 5bit sub-DAC ( X , Y, or Z), while at the same time, the bottom plate of is connected to the output of the gain amplifier. , 1997]. In this way, the errors caused by capacitor parasitics and signaldependent charge injections can be greatly reduced.

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